Modern electronic systems are often composed of integrated circuits (ICs) fabricated on small rectangular portions of flat wafers. The small rectangular portions of the wafers are commonly known as dies and as chips. Individual components of a given integrated circuit are formed by the addition of successive thin planer layers of various materials and the subsequent removal of portions of the added layers which results in the formation of patterned layers on the wafers. Selected areas of particular patterned layers are then electrically coupled together via contact areas between those layers to form the components and the circuits.
There is a continuing trend toward manufacturing integrated circuits with higher component densities. This down-scaling of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher cost efficiency in IC fabrication by providing more circuits on a die and/or more die per semiconductor wafer. Smaller feature sizes of necessity mean contacts having smaller cross-sectional areas.
An important technology used in the construction of integrated circuits is that of Complementary Metal-Oxide-Semiconductor (CMOS) technology due primarily to its low power consumption. In typical digital designs CMOS employs complementary pairs of p-type and n-type metal-oxide-semiconductor field effect transistors (MOSFETs) for logic functions. Since one transistor of the pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic such as transistor-transistor logic (TTL) or NMOS logic, which normally have some standing current even when not changing state.